The present invention relates to the field of instruction-controlled digital computers and specifically to program event recording in high-speed data processing systems. Instruction-controlled digital computers operate upon data to carry out desired data manipulations. A group of instructions form a program. The program normally has its instructions sequentially executed, one or more at a time, to carry out a complete data manipulation. In fetching and storing information during the operation of the data processing system, programs and control circuitry operating in the system make reference to system storage using storage addresses.
To completely specify a storage access, the number(L' ) of contiguous bytes to be fetched or stored is given as well as the lowest address, that is the system address or effective address (E), of the bytes being accessed. If L is defined to be equal to the number of bytes being accessed minus one (L'-1), then the address of the highest byte being referenced on one access is the sum, E+L. The address of this highest byte is known as the upper address(UA). The effective address E and the upper address UA define the address operation range.
Frequently it is desired to monitor the data processing system and to determine when the system has a storage access which falls within a range of addresses specified by a lower bound and an upper bound called the program event range(PER range). For example, when debugging programs, programmers find it particularly useful to determine when an access to storage falls between the programmer-specified upper and lower limits.
Prior art program event recording has generally required a degrading of system performance whenever it is in operation. The degrading of system performance, of course, is undesirable. There is a need, therefore, for economical program event recorders which reduce or eliminate the degrading of system performance.